This invention relates to a phase locked loop circuit.
Referring to FIG. 1 of the drawings, a conventional phase locked loop circuit (PLL) comprises a phase comparator 10, a low pass filter 14, a voltage controlled oscillator (VCO) 18 and a divider 22. A reference signal source, such as a crystal oscillator 26, provides a reference signal at a frequency FR to one input of the phase comparator and the output of the divider is connected to the other input of the phase comparator. The phase comparator generates as its output signal a pulse train in which the pulses have a duration that depends on the phase difference between the output signal of the divider and the reference signal. The low pass filter 14 integrates the pulse signal of the phase comparator over a period substantially greater than the interval between pulses and provides a DC output signal at a voltage that depends on the duration of the pulses provided by the phase comparator. The VCO generates an output signal at a frequency that is a function of the voltage of the DC signal provided by the low pass filter. The divider divides the frequency of the VCO output signal by a selected factor D. The output signal of the divider is fed back to the second input of the phase comparator. The PLL forces the feedback signal into phase with the reference signal by causing the VCO to oscillate at a frequency FR*D. For example, in the event that the reference signal is a 10 MHz signal and the divider divides by 10, the VCO output signal is at a frequency of 100 MHz.
In the case of the conventional PLL, as shown in FIG. 1, the pulses produced by the phase comparator occur at the reference frequency FR and the low pass filter 14 passes signal energy at the reference frequency to the VCO. Accordingly the energy spectrum of the output signal of the VCO has a primary lobe at the frequency FR*D and also includes secondary lobes at the frequencies FR*D+/−FR. It is desirable to minimize energy at frequencies other than FR*D.
One technique for reducing the height of the secondary lobes would be to employ a fractional N PLL. For example, one could control the divider to divide part of the time by the factor 9.9, part of the time by the factor 10 and part of the time by the factor 10.1, so that the average factor is 10, and in this case the energy of the secondary lobes would be distributed over multiple lobes, each of which would contain less energy than the secondary lobes in the case that the factor were 10 at all times. However, this solution is subject to the disadvantage that the primary lobe is wider and lower than if the factor were 10 at all times.